1. Field of the Invention
The present invention relates generally to an apparatus for processing analog singals representative of a continuously changing and, prehaps, toxic chemical environment, but more specifically the present invention relations to an apparatus having a unique parallel pipeline processor type of architecture for processing a large amount of analog data.
2. Description of the Prior Art
In the field of high performance digital and analog computation, there have been many techniques developed for improving the speed and resolution at which a computer can execute instructions and process data. One of the most well known approaches known in the prior art is to simply improve the performance of the computer by optimizing the system architecture.
A particular example of such an advanced approach to improving the speed at which computers can process instructions is the development of the pipeline processor. These processors can perform many instructions at very high speeds because of their internal organization. In the generic sense, a pipeline processor actually performs several operations on several different instructions simultaneously. For example, one instruction might call for an operation upon two operands contained within the main memory of the computer. These operands might be fetched from the main memory during the same period of time that a second instruction was being decoded to determine its type as well as its data requirements. Still a third instruction might be nearing its completion, all in the same machine cycle.
Although the generic pipeline processor is highly efficient as compared to other data processors, the pipeline data processor has an inherent problem which prevents maximum utilization of its data processing capability. Due to program dependencies, even a pipeline processor can be put into a waiting state while data is being fetched from the main memory. During these waiting periods, even a pipeline processor can not utilize all of its available processing capability. Some of these inherent problems with the generic pipeline processor have been solved and their solution is disclosed in the U.S. Pat. No. 3,771,138, filed Aug. 31, 1971, to Celtruda et al, entitled, "Apparatus and Method for Serializing Instructions From Two Independent Instruction Streams", patent granted Nov. 6, 1973. Accordingly, Celtruda et al is of general interest as to generic pipeline architecture.
Since a pipeline processor is a very complicated data processing unit, designing a system with a pipeline processor capable of processing instructions simultaneously from two different instruction streams requires a certain amount of sophisticated hardware to perform the buffer and the selection functions. Consequently, there is a need in the prior art to configure a unique pipeline processor containing the required circuitry to perform the instruction interleaving function which is required in order to share the pipeline processor between two instruction streams, i.e., split sections.
The parallel pipeline processor, according to the present invention is divided into separate functional and physical modules. By control of a control module portion, the results of one module are fed to the next in a cascaded manner. This pipelining allows for a higher throughput speed in that each module is always computing data based on results obtained by a previous module rather than one module during all of the calculations in a serial fashion. The processor itself is essentially a micro-program device.
The prior art, as indicated hereinabove, included many advances in processors of the pipeline type, including those that are configured to increase the processing of data. However, insofar as can be determined, no prior art pipeline processor incorporates all of the features and advantages of the present invention.